리벨리온 RTL Engineer

한 줄 요약

리벨리온 RTL Engineer — 리벨리온 · Rebellions | Korea. 현재 상태: 진행·예정.

정보 갱신일 2026-10-21

조건·일정 확인

기관·대학

리벨리온

지역·근무지

Rebellions | Korea

학력

석사 이상

담당 업무

• Interconnect RTL Design: design and implement the D2D interconnect subsystem — transaction management and datapath, link-level reliability (retry/replay, CRC, FEC), and built-in test, debug, and monitoring structures (traffic generation/comparison, loopback, per-port counters, performance monitors).
• NPU SoC System View: work with a system-level view of the NPU SoC. The D2D subsystem carries accelerator traffic, so its microarchitecture follows from how compute, memory hierarchy, and NoC move data. You will build that view here, alongside the architect.
• Microarchitecture Definition: concretize the interconnect microarchitecture together with the architect — including the areas that industry specs leave under-defined.
• Standard-Spec-Based Design: design against open standards (UCIe, CHI, CHI C2C and related specs) and integrate vendor controller/PHY IP through standard interfaces (e.g., RDI/FDI/AXI) and Rebellions in-house NoC interface.
• Cross-Functional Collaboration: partner with verification, SoC integration, firmware (register map / control interface), and PSI teams to make the subsystem work in the real system.
• Silicon Bring-up: participate in D2D link bring-up and support post-silicon debugging down to RTL simulation when issues go deep.
• 채용 관련 문의사항은 아래 메일 주소로 문의바랍니다.
• recruit@rebellions.ai

지원 자격

• Minimum 6+ years of combined experience in RTL design using SystemVerilog/Verilog (M.S. counted as 2 years, Ph.D. as 4 years toward this total). Fewer years with clear depth in interconnect or link-layer RTL is also worth a conversation.
• Block Ownership: you have owned at least one non-trivial block end to end in RTL. Prior architecture-definition experience is welcome but not required — you will define microarchitecture here with the architect beside you, not alone.
• Simulation & Debugging: proficiency in a logic simulation tool (VCS or Xcelium) with the ability to root-cause complex RTL issues.
• Quality Toolchain: familiarity with industry-standard quality flows — Lint, CDC, and Synthesis at minimum.
• Communication & collaboration: . strong, collaborative cross-functional work — root-causing a chiplet issue spans architecture, verification, firmware, PSI, and vendor teams, so we value engineers who debug with data rather than blame and own their mistakes honestly.

우대 사항

• Tape-out & Silicon Bring-up: experience carrying a design through tape-out and into post-silicon debug. Valuable here, but not a requirement — the role includes bring-up, so you can also learn it on this project.
• Interconnect Protocols: working knowledge of AMBA (AXI/ACE) or CHI, or any packetized on-chip protocol — transaction ordering, outstanding-transaction management, and credit-based flow control.
• Clock, Reset & Low-Power Infrastructure: clock domain crossing, reset domain crossing, and power/clock gating in a multi-domain design.
• DFT: scan insertion, compression, and DFT-aware RTL practices.
• SerDes / high-speed PHY: working understanding of SerDes-based high-speed links — PCS/PMA partitioning, equalization, clock/data recovery, and link training — and the digital logic that interfaces to a SerDes PHY.

공식 출처와 다음 단계

원천 정보 갱신: 2026. 10. 21. PM 5:06

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관련 정보

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