Cadence Design Systems Product Engineering Architect – High-Speed IP PHY

한 줄 요약

Cadence Design Systems Product Engineering Architect – High-Speed IP PHY — Cadence Design Systems · GYEONGGI-DO (Seoul) · Full time. 현재 상태: 진행·예정.

정보 갱신일 2026-10-21

조건·일정 확인

기관·대학

Cadence Design Systems

지역·근무지

GYEONGGI-DO (Seoul)

고용 형태

Full time

학력

학사 이상

담당 업무

• Act as the primary product engineering owner for high-speed interface IPs (PCIe, UCIE, Ethernet, USB, DDR, LPDDR, GDDR, HBM) at the customer level
• Lead customer engagements, drive technical discussions, design reviews, and deployment strategy
• Own and drive resolution of complex subsystem integration and implementation issues
• Lead SoC integration reviews covering PHY and controller subsystems
• Provide technical leadership for RTL, gate-level simulations, and timing closure strategies
• Define and drive improvements to integration methodologies, checklists, and customer collateral
• Lead post-silicon bring-up and debug activities, ensuring successful customer deployment
• Collaborate cross-functionally with R&D, validation, and applications teams to deliver product readiness
• Drive continuous improvement in customer experience, turnaround time, and engineering quality
• Mentor and lead all team members and provide technical guidance across projects as needed
• Work with global product engineering management to define, develop, and consistently execute best-in-class customer support procedures
• Leverage AI tools to improve debug efficiency, data analysis, and decision-making

지원 자격

• Strong experience with high-speed interface IP
• Deep understanding of RTL design, gate-level verification, and simulation methodologies
• Experience with synthesis, STA, and timing closure; backend knowledge is a plus
• Familiarity with DFT methodologies, test flows, and system validation approaches
• Bachelor’s in electrical engineering, Computer Engineering, or related field with 15+ years, Master’s with 12+ years, or PhD with 10+ years of relevant experience
• Proven ability to solve complex technical problems and drive root cause to closure
• Experience leading cross-functional technical efforts across design, validation, and customer teams
• Strong communication skills with ability to influence customer and internal stakeholders
• Experience managing multiple priorities, escalations, and technical reviews
• Demonstrated ability to represent the organization in customer-facing technical roles
• Strong ownership mindset and ability to drive deliverables independently
• Demonstrated ability to communicate and coordinate well with direct reports in local team and supervising management within a larger organization

우대 사항

• Experience with memory and/or high-speed communication interfaces (DDR, LPDDR, PCIe, Ethernet, UCIe, USB)
• Understanding of analog/mixed-signal design practices
• Experience in customer-facing silicon debug and bring-up environments
• Familiarity with AI-assisted workflows and data-driven debug techniques

공식 출처와 다음 단계

원천 정보 갱신: 2026. 10. 21. PM 5:06

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