퓨리오사AI Hardware - Signal/Power Integrity Engineer (On-/Off-Chip)

한 줄 요약

퓨리오사AI Hardware - Signal/Power Integrity Engineer (On-/Off-Chip) — 퓨리오사AI · Seoul, South Korea. 현재 상태: 진행·예정.

정보 갱신일 2026-10-21

조건·일정 확인

기관·대학

퓨리오사AI

지역·근무지

Seoul, South Korea

학력

학사 이상

담당 업무

• Define SI/PI requirements based on IP and system-level specifications.
• Perform SI/PI simulations at electromagnetic (EM), circuit, and system levels.
• Develop SI/PI methodologies for advanced packaging technologies such as chiplet, 3D-IC, D2D (die-to-die), and C2C (chip-to-chip) interfaces.
• Cover SI/PI analysis and optimization at the full system level, including on-chip, package, and PCB domains.
• Provide design guidance on stack-up, interconnect routing, PDN architecture, decoupling strategy, and component selection.
• Collaborate with silicon, package, and board teams to ensure accurate measurement-simulation correlation and system-level robustness.
• Support debug and bring-up efforts in the lab when needed.
• Work with internal teams and partners to co-optimize SI/PI solutions.

지원 자격

• BS or MS in Electrical Engineering, Physics, or a related field.
• 8+ years of experience in component- and system-level SI/PI analysis.
• Solid understanding of SI/PI fundamentals and methodologies.
• Hands-on experience with lab instruments such as VNA, TDR, and real-time oscilloscopes.
• Proficient in EDA tools such as SIwave, HFSS, ADS, HSPICE, Allegro, RedHwak-SC, SC-ET, or RedHawk-3DIC.

우대 사항

• PhD in Electrical Engineering, Physics, or a related field with 5+ years of relevant industry experience.
• Candidates with one or more of the following experiences will be given strong consideration:
• SI/PI analysis and optimization for high-speed digital systems and standard interfaces (e.g., PCIe, DDR, Ethernet)
• Model and analyze complex 3D structures using EM simulation tools
• On-chip Backend sign-off (Static/Dynamic IR, EM)
• On-/Off-chip PDN modeling and budgeting
• On-chip glitch/jitter/DVD analysis and sign-off methodology, including cross-talk, TSV uncertainty, and multi-corner/process derating
• Early-stage reference clock jitter estimation and sign-off methodology development
• Experience with on-chip clock sign-off, including clock design guide, 3DIC jitter derating, and multi-corner/process variation analysis.
• talent@furiosa.ai

공식 출처와 다음 단계

원천 정보 갱신: 2026. 10. 21. PM 5:06

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