딥엑스 [HW] GPU Subsystem Engineer

한 줄 요약

딥엑스 [HW] GPU Subsystem Engineer — 딥엑스 · ㈜딥엑스 · 경력 3~30년 · 정규직. 현재 상태: 진행·예정.

정보 갱신일 2026-10-21

조건·일정 확인

기관·대학

딥엑스

지역·근무지

㈜딥엑스

고용 형태

정규직

경력

경력 3~30년

학력

공식 공고 확인

담당 업무

• □ IP Integration & RTL Design: Lead the integration of high-performance GPU IPs (e.g., ARM Mali, Imagination, or proprietary cores) into the SoC top-level environment.
• □ Interconnect Architecture: Design and optimize data paths between the GPU and the System-on-Chip using AMBA protocols (AXI, ACE, CHI) and Network-on-Chip (NoC) solutions.
• □ Performance Optimization: Analyze GPU throughput and latency to minimize bottlenecks in data-heavy AI and graphics workloads.
• □ System Validation: Conduct RTL-level verification, Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure robust hardware stability.
• □ Power & Area Management: Collaborate with the physical design team to optimize the GPU's power consumption (UPF/CPF) and silicon footprint for edge devices.
• □ Hardware-Software Co-design: Work with the firmware and driver teams to define GPU memory maps, interrupt handling, and power-up sequences.

지원 자격

• Expertise in Verilog or SystemVerilog.
• Deep understanding of AMBA bus architectures (specifically AXI4 and ACE for cache coherency).
• Familiarity with GPU pipeline architectures and memory management units (IOMMU/SMMU).

우대 사항

• □ Experience of FPGA Implementation
• □ Graphics Knowledge: Familiarity with graphics APIs (OpenGL ES, Vulkan, or OpenCL) and how hardware accelerates these standards.
• □ Cache Coherency: Experience with hardware-managed cache coherency between CPUs, GPUs, and NPUs.
• □ Advanced Nodes: Proven track record of tape-outs in advanced process nodes (7nm, 5nm, or below).
• □ Post-Silicon Support: Experience in silicon bring-up and debugging GPU-related issues in the lab.
• □ Communication: Strong technical English communication skills for collaborating with global IP vendors.

공식 출처와 다음 단계

원천 정보 갱신: 2026. 10. 21. PM 5:06

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