딥엑스 [HW] CPU Subsystem Engineer

한 줄 요약

딥엑스 [HW] CPU Subsystem Engineer — 딥엑스 · ㈜딥엑스 · 경력 5~30년 · 정규직. 현재 상태: 진행·예정.

정보 갱신일 2026-10-21

조건·일정 확인

기관·대학

딥엑스

지역·근무지

㈜딥엑스

고용 형태

정규직

경력

경력 5~30년

학력

공식 공고 확인

담당 업무

• □ Subsystem Integration: Integrate ARM or RISC-V based CPU IP into AI SoC platforms, focusing on top-level connectivity and hierarchy.
• □ Bus & Interconnect Design: Design and configure high-speed on-chip interconnects (NoC/NIC) using protocols such as AMBA (AXI, ACE, CHI) to ensure low-latency data paths.
• □ Memory Hierarchy Management: Define and optimize the integration of L2/L3 caches, Snoop Control Units (SCU), and memory controllers.
• □ Architecture Validation: Perform RTL-level integration checks, linting, and CDC (Clock Domain Crossing) analysis to ensure design integrity.
• □ Performance Tuning: Collaborate with the Architecture team to analyze and resolve system bottlenecks related to CPU-to-NPU communication.
• □ Cross-functional Collaboration: Work closely with Front-end/Back-end teams and Software/Firmware teams to define boot sequences and power management schemes.

우대 사항

• □ Experience of FPGA Implementation
• □ NoC Expertise: Hands-on experience with Network-on-Chip (NoC) IP (e.g., Arteris, ARM CoreLink).
• □ Low Power Design: Knowledge of UPF/CPF based power intent and multi-voltage domain integration.
• □ Security Integration: Experience integrating hardware security modules (TrustZone, Root of Trust).
• □ Advanced Nodes: Experience in advanced process nodes (5nm, 4nm, or below).
• □ Problem Solving: A proactive mindset with the ability to navigate the complexities of cutting-edge AI hardware.

공식 출처와 다음 단계

원천 정보 갱신: 2026. 10. 21. PM 5:06

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