BRIDGELYT · RESEARCH & OPPORTUNITIES
딥엑스 [HW] High-Speed Interface SI/PI Engineer
딥엑스 [HW] High-Speed Interface SI/PI Engineer — ㈜딥엑스 · 경력 3~30년 · 정규직. 담당 업무·지원 자격·마감일과 공식 지원 링크를 확인하세요.
진행·예정 · 출처에서 확인한 정보이며 최종 조건은 공식 원문을 확인하세요.
한 줄 요약
딥엑스 [HW] High-Speed Interface SI/PI Engineer — 딥엑스 · ㈜딥엑스 · 경력 3~30년 · 정규직. 현재 상태: 진행·예정.
정보 갱신일 2026-10-21
조건·일정 확인
- 기관·대학
- 딥엑스
- 지역·근무지
- ㈜딥엑스
- 고용 형태
- 정규직
- 경력
- 경력 3~30년
- 학력
- 석사 이상
담당 업무
- □ PDN & Power Integrity Analysis: Perform comprehensive PDN analysis including DC/AC frequency-domain analysis (Target Impedance profiling) and time-domain transient simulations to guarantee stable power delivery from the VRM to the die.
- □ NPU Transient Power Management: Analyze and mitigate inrush current and severe $di/dt$ noise caused by the simultaneous switching of massive digital blocks (e.g., MAC arrays) in NPU architectures. Establish and optimize on-die, package, and board-level decoupling capacitor (Decap) strategies to prevent Dynamic Voltage Drop (DVD) and Ground Bounce.
- □ SI Modeling & Simulation: Perform comprehensive Signal Integrity (SI) simulations for high-speed interfaces (LPDDR4/5, PCIe Gen4/5, MIPI, etc.), ensuring optimal eye diagrams and jitter margins.
- □ System-Level Co-Simulation: Conduct Chip-Package-Board (CPB) co-simulations using CPM (Chip Power Model) or equivalent methodologies to evaluate and mitigate cross-talk, EMI/EMC issues, thermal-electrical coupling, and IR drop.
- □ Design Optimization: Establish design guides for PCB/Package stack-ups, high-speed routing, and optimal Decap placement (using optimization tools) to meet strict noise and jitter budgets.
- □ Validation & Correlation: Collaborate with the hardware team to perform lab measurements (using Oscilloscopes, VNA, TDR, and active probes) and correlate physical data with simulation results.
우대 사항
- □ Master’s or Ph.D. with a focus on Electromagnetics, Power Electronics, or High-Speed Circuit Design.
- □ NPU/GPU Power Design: Direct experience resolving extreme transient power challenges in highly parallel computing architectures like NPUs, GPUs, or high-end SoCs.
- □ Specific Protocol Expertise: Experience with LPDDR5x or PCIe Gen5/6 interface design and verification.
- □ Packaging Knowledge: Understanding of advanced packaging technologies (Flip-chip, 2.5D/3D IC, SiP) and their impact on signal and power integrity.
- □ Scripting Skills: Proficiency in Python or MATLAB for automation of simulation workflows and data post-processing.
- □ Communication: Strong problem-solving skills and the ability to communicate technical concepts clearly across multi-functional teams (SoC Design, Package, and System).
공식 출처와 다음 단계
공식 원문 확인원천 정보 갱신: 2026. 10. 21. PM 5:06
본문에 없는 자격·금액·일정은 임의로 보완하지 않습니다. 원문과 담당 기관에서 확인하세요.
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