딥엑스 [HW] SoC Bus Verification Engineer

한 줄 요약

딥엑스 [HW] SoC Bus Verification Engineer — 딥엑스 · ㈜딥엑스 · 경력 3~20년 · 정규직. 현재 상태: 진행·예정.

정보 갱신일 2026-10-21

조건·일정 확인

기관·대학

딥엑스

지역·근무지

㈜딥엑스

고용 형태

정규직

경력

경력 3~20년

학력

공식 공고 확인

담당 업무

• □ Verification Strategy: Define and develop comprehensive verification plans for complex SoC Interconnects and Bus structures based on architectural specifications.
• □ Testbench Development: Build and maintain advanced verification environments using UVM (Universal Verification Methodology) and SystemVerilog.
• □ Protocol Validation: Verify high-speed bus protocols (AMBA AXI, CHI, ACE) to ensure data integrity, cache coherency, and protocol compliance.
• □ Performance Verification: Analyze bus performance metrics including throughput, latency, and arbitration efficiency to identify and resolve bottlenecks.
• □ Debug & Analysis: Conduct deep-dive debugging of complex RTL issues and perform code/functional coverage analysis to achieve 100% verification closure.
• □ Gate-Level Simulation: Execute and verify GLS (Gate-Level Simulation) to ensure timing and functional correctness after synthesis.

우대 사항

• □ NoC Experience: Experience verifying Network-on-Chip (NoC) IPs (e.g., Arteris, Netspeed, or Synopsys).
• □ Scripting Skills: Proficiency in scripting languages such as Python, Perl, or Tcl for automation and result analysis.
• □ Coherency Knowledge: Experience with multi-core cache coherency and memory consistency models.
• □ Formal Verification: Familiarity with Formal Verification tools and property checking (SVA).
• □ AI Hardware Interest: Experience or strong interest in the data-flow requirements of NPU and AI hardware accelerators.

공식 출처와 다음 단계

원천 정보 갱신: 2026. 10. 21. PM 5:06

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